Generally, semiconductor devices have at least one fuse box. The fuse boxes serve to replace one or more failed cells that do not operate during a driving test of a semiconductor device with redundant cells. The replacement of failed cells with redundant cells is performed by disabling the failed cells through a repair process that cuts a fuse in the fuse box relative to the failed cells with laser beams and selecting the redundant cells. The repair process comprises irradiating laser beams to blow predetermined fuses such that the redundant cell has the address of the failed cell in write and read modes. The fuse box may comprise a fuse region in which the fuses are disposed and a guard region surrounding the fuse region. The guard region may have a moisture-proof dam for preventing penetration of moisture from the fuse region into the semiconductor device.
A method of fabricating a fuse is disclosed by Sato et al. in U.S. Patent Publication No. 2005/0161766 A1 entitled “Semiconductor Device and Method for Fabricating the Same.”
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method of fabricating a semiconductor device having a moisture-proof dam.
Referring to FIG. 1A, an interlayer insulating layer 5 may be formed on a semiconductor substrate 1. A fuse contact plug 10 passing through the interlayer insulating layer 5 may be formed. A barrier layer, a fuse metal layer and a capping layer are sequentially formed on the substrate having the fuse contact plug 10. The barrier layer may be a titanium nitride layer, the fuse metal layer may be an aluminum (Al) layer, and the capping layer may be formed by stacking titanium and titanium nitride layers. The capping layer, the fuse metal layer and the barrier layer are sequentially patterned, thereby forming a first barrier pattern 13a, a fuse 15a and a first capping pattern 18a which are sequentially stacked in a fuse region, and forming a second barrier pattern 13b, a fuse guard dam 15b and a second capping pattern 18b which are sequentially stacked around the fuse region.
Referring to FIG. 1B, an intermetal insulating layer 25 may be formed on the substrate having the first barrier pattern 13a, the fuse 15a and the first capping pattern 18a. The intermetal insulating layer 25 may be formed of boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), spin-on-glass (SOG), tetra ethyl ortho silicate (TEOS), or undoped silicate glass (USG). The BPSG, PSG, SOG, TEOS and USG layers have excellent step coverage, and strong moisture absorption.
A via dam 27 passing through the intermetal insulating layer 25 and contacting the second capping pattern 15b may be formed. The via dam 27 may be formed of an Al layer. Also, the via dam 27 may comprise a titanium nitride layer covering a bottom surface and sidewalls of the Al layer.
An upper guard dam 30 covering the via dam 27 may be formed on the intermetal insulating layer 25. The upper guard dam 30 may be formed of a titanium nitride layer, an aluminum layer, and a titanium and titanium nitride layer which are sequentially stacked. A protection insulating layer 35 may be formed on the substrate having the upper guard dam 30.
Referring to FIG. 1C, the protection insulating layer 35 and the intermetal insulating layer 25 are patterned to form a fuse window 36 exposing the fuse 15a. In general, the fuse window 36 may be formed to expose the middle part of the fuse 15a as illustrated in FIG. 1C. In result, during the formation of the fuse window 36, the first capping pattern 18a remains on both ends of the fuse 15a. Since the intermetal insulating layer 25 has strong moisture absorption, external moisture, for example, moisture in the air, may be introduced into an interface of the first capping pattern 18a from the outside along a path represented by arrow “A” through the fuse window 36.
Referring to FIG. 1D, the fuse 15a exposed through the fuse window 36 and the barrier pattern 13a under the fuse 15a may be cut by laser beams in the repair process.
When external moisture is introduced into the interface of the first capping pattern 18a from the outside through the fuse window 36, the first capping pattern 18a formed of a titanium and titanium nitride layer may expand as a result of the moisture. For example, the moisture may expand due to high temperatures during semiconductor manufacturing or during testing. In addition, oxygen in the moisture may react with titanium included in the first capping pattern 18a, which may result in the expansion of the first capping pattern 18a. As a result, an expanded capping pattern 18c may be formed as illustrated in FIG. 1D.
Accordingly, the expanded capping pattern 18c may apply more stress to the intermetal insulating layer 25 disposed thereon. For this reason, a crack C may occur in the intermetal insulating layer 25 adjacent to the expanded capping pattern 18c, and may extend to the via dam 27 adjacent to the upper guard dam 30. The crack C may extend to the interface between the via dam 27 and the upper guard dam 30.
The crack C may serve as an inflow path of moisture or contaminated materials, which may lead to corrosion of interconnections and increase in leakage current. As such, the moisture or contaminated materials introduced through the crack C may cause malfunction of the semiconductor device.